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High-Level Synthesis Made Easy Book Overview

This book is intended to teach anyone, either someone with deep hardware development skills, or someone with little prior hardware design knowledge alike to learn how to design and verify dedicated hardware modules using HLS. HLS converts untimed or partially timed behavioral descriptions into efficient hardware descriptions in either Verilog or VHDL that can in turn be further synthesized into gate netlists through logic synthesis. The word efficient is extremely important as nobody would build a integrated circuit (IC) using HLS if the generated circuit is larger, slower and consumes more power than using traditional methods based on low-level Hardware Description Languages (HDLs).

The book will start by describing what HLS is and its main benefits. It will then cover the theory behind HLS. Basically I will answer the question of how an untimed behavioral description that was originally intended to be compiled to machine code to be executed by a Central Processing Unit (CPU) is converted into a dedicated hardware unit. The book will cover different types of optimizations to allow the designer to generated the hardware circuit within the intended constraints, and finally it will cover different input languages and how they differ. In particular ANSI-C and SystemC. I share this book with the hope that you might find it useful. Happy reading.

Chapter One

Introduction: What is High-Level Synthesis.

Chapter Two

Hardware Platforms: From ASIC to FPGA.

Chapter Three

High-Level Synthesis. Learn the principles behind HLS.

Chapter Four

Verification of HLS design. From untimed to cycle-accurate verification.

Chapter Five

High-Level Synthesis optimizations. Unroll loops, pipeline them or inline functions through synthesis directives.

Chapter Six

High-Level Synthesis Design Space Exploration. Learn how to automatically create functional equivalent hardware designs from the same behavioral description.

Chapter Seven

Input Languages. From Matlab, OpenCL to ANSI C, C++ and SystemC.

Chapter Eight

SystemC. Learn why SystemC is often preferred for HLS.

Chapter Nine

Commercial High-Level Synthesis Tools.

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High-Level Synthesis: Applications Book Overview

This book is intended as a continuation of that book and goes over some unique advantages of raising the level of VLSI design abstraction from the Register Transfer Level (RTL) to the behavioral level and more importantly how to leverage these advantaged in different domains. In particular, low-power design, fault-tolerance, and hardware security. I also cover how legacy hardware circuits given in Verilog or VHDL can be modernize thought HLS.

Much of the work presented in this book was done by graduate students at my lab during the past 15 years. I have to therefore dearly thank them for it.

The book will start by describing reviewing what HLS is and where it fits in a typical VLSI design flow. It will then cover low-power design, thermal-aware design, hardware security, fault tolerance and finally covering how HLS can help to modernize legacy hardware designs.

Chapter One

VLSI Design Overview.

Chapter Two

HLS: One Description, Infinite Implementations.

Chapter Three

Low Power Design in High-Level Synthesis.

Chapter Four

Temperature Control in HLS: Is this even possible?

Chapter Five

Hardware Security.

Chapter Six

Fault Tolerance.

Chapter Seven

Modernizing Legacy Hardware Designs.

Chapter Eight

Wrapping up.

High-Level Synthesis Workshop

The following video gives you an oveview of what HLS is and how it works.

About The Author

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Benjamin Carrion Schaefer

Dr. Carrion Schaefer has over 20 years of academic and industrial experience in the design of hardware systems, FPGA and ASICs as well as in the development of commercial HLS tools. From 2007 to 2012 he was a member of the NEC teams that developed NEC's HLS tool CyberWorkBench. He recently created highX Technologies. A company dedicated to making hardware design easier by providing highly customizable Behavioral IPs for High-Level Synthesis.

He currently serves as associate Professor at The University of Texas at Dallas at the department of Electrical and Computer Engineering (ECE) where he has established the Design and Reconfigurable Computing Laboratory (DARClab). At UTD he investigates how to leverage the advantages of using of High-Level Synthesis (HLS) instead of traditional hardware decription languages such as Verilog or VHDL, and how to address new issues that arise when using HLS. He also served multiple years at OSCI's (now Accellera's) SystemC synthesizable subset working group as one of the members drafting the latests draft (version 1.4).

The author, holds a Ph.D. from The University of Birmingham, UK and an MBA from McGill University, Canada.

Book Price

These books are free for personal use. Although I have done by best effort in preparing them. I nor the publisher make no representation or warranties with respect to the accuracy, applicability, fitness or completeness of the contents of these books. The information contain in these books is strictly for educational purposes. Therefore, if you wish to apply ideas contained in this book, you are taking full responsability for your actions.

You can cite these books as follows:

@book{hlsbook,
author = {{B. Carrion Schaefer}},
year = {2023},
title = {{High-Level Synthesis Made Easy}},
publisher = {highX Technologies},
edition = {1st},
url = {https://www.hlsbook.com}
}

@book{hlsbook_applications,
author = {{B. Carrion Schaefer}},
year = {2025},
title = {{High-Level Synthesis: Applications}},
publisher = {highX Technologies},
edition = {1st},
url = {https://www.hlsbook.com}
}

You can also purchase a hard copy through Amazon HLS Made Easy and HLS: Applications

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